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EL5625
Data Sheet February 28, 2006 FN7488.0
PRELIMINARY
Programmable 18-Channel Gamma with 1-Channel VCOM with Reference
The EL5625 represents a high integration programmable buffer solution from Intersil. The device integrates 18channels of programmable buffers, with a single programmable VCOM, a reference output, and a supply side LDO. The 18-channel programmable buffers have 11-bit resolution and rail-to-rail outputs. Each output is capable of driving 15mA continuous. The VCOM output also features 11-bits of resolution. The generated voltage is connected to the non-inverting input of the integrated VCOM amplifier. This amplifier has a shortcircuit current of 1A, 100mA continuous. The integrated low drop-out regulator is used, in conjunction with an external transistor, to provide a solid supply voltage to the device. It features 200mV minimum drop-out and has very good load regulation for the cleanest gamma and VCOM outputs. The EL5625 also includes over-temperature protection and is available in a 38-pin QFN package.
Features
* 18-channel programmable gamma - Rail-to-rail * Single VCOM amplifier - 1A peak output * 11-bit resolution per output * Accuracy 0.5% * Integrated supply LDO - Low drop out - 200mV * Integrated reference - Very accurate - 0.75% * +7V to +16V supply * Thermal protection * 38-pin QFN * Pb-Free plus anneal available (RoHS compliant)
Applications
* LCD-TVs * Flat panel monitors * TFT-LCD displays
Pinout
EL5625 (38-PIN QFN) TOP VIEW
33 OUTG 38 OUTB 37 OUTC 36 OUTD 32 OUTH 35 OUTE 34 OUTF
Ordering Information
PART NUMBER (See Note) EL5625ILZ
31 OUTI 30 VS 29 GND 28 CAP 27 LDO_OUT
PACKAGE (Pb-Free) 38-Pin QFN 38-Pin QFN
TAPE & REEL 13"
PKG. DWG. # MDP0046 MDP0046
OUTA 1 LDO_COMP 2 LDO_IN 3 VSD 4 SDI 5 SCLK 6 ENA 7 SDO 8 RD_WRBAR 9 EXT_OSC 10 RESET 11 OUTR 12 OUTQ 13 OUTP 14 OUTO 15 OUTN 16 OUTM 17 OUTL 18 OUTK 19 THERMAL PAD
EL5625ILZ-T13
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
26 REFH 25 REFL 24 INNCOM 23 GND 22 OUTCOM 21 VS 20 OUTJ
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5625
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS and GND. . . . . . 4.5V(min) to 18V(max) Supply Voltage between VSD and GND 3V(min) to VS and +7(max) Maximum Continuous Output Current (Gamma) . . . . . . . . . . . 15mA Maximum Continuous Output Current (VCOM) . . . . . . . . . . . 100mA Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY IS ISD ANALOG VOL Supply Current
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
No load
11 1.1
15 1.35
mA mA
Digital Supply Current
Output Swing Low (Chan 1-16) Output Swing Low (Chan 17, 18)
Sinking 5mA (VREFH = 15V, VREFL = 0)
100 50
200 150
mV mV V V mA dB dB ms mV mV
VOH
Output Swing High (Chan 1, 2) Output Swing High (Chan 3-18)
Sourcing 5mA (VREFH = 15V, VREFL = 0)
14.85 14.8
14.95 14.9 130 70 60 4
ISC PSRR
Short Circuit Current Power Supply Rejection Ratio
RL = 10 VS+ is moved from 14V to 16V VCOM
100 50 45
tD VAC VMIS VDROOP RINH REG BG DIGITAL VIH VIL FCLK tS tH tLC tCE tDCO RSDIN TPULSE Duty Cycle
Program to Out Delay Accuracy Referred to the Ideal Value Channel to Channel Mismatch Droop Voltage Input Resistance @ VREFH, VREFL Load Regulation Band Gap IOUT = 5mA step 1.227 25 Code = 512 Code = 512
20 2 1 32 1 1.242 3 1.257 2
mV/ms k mV/mA V
Logic 1 Input Voltage Logic 0 Input Voltage Clock Frequency Setup Time Hold Time Load to Clock Time Clock to Load Line Clock to Out Delay Time SDIN Input Resistance Minimum Pulse Width for EXT_OSC Signal Duty Cycle for EXT_OSC Signal Negative edge of SCLK
2 1 5 20 20 20 20 10 1 5 50
V V MHz ns ns ns ns ns G s %
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EL5625
Electrical Specifications
PARAMETER F_OSC INL DNL VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = 25C, unless otherwise specified. (Continued) CONDITIONS OSC_Select = 0 MIN TYP 21 1.3 0.5 MAX UNIT kHz LSB LSB
DESCRIPTION Internal Refresh Oscillator Frequency Integral Nonlinearity Error Differential Nonlinearity Error
VCOM CHARACTERISTICS BW SR ISC Bandwidth of VCOM Slew Rate Short-Circuit Current 5 10 9 1000 MHz V/s mA
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FN7488.0 February 28, 2006
EL5625 Typical Application Diagram
LDO_IN +15V 0.1F LDO_COMP +5V 0.1F VSD + V=1.242 REFH HIGH REFERENCE VOLTAGE +13V 0.1F 19 CHANNEL REGISTERS VOLTAGE SOURCES OUTA COLUMN (SOURCE) DRIVER VS + LDO_OUT
OUTB
OUTQ LCD PANEL RESET OUTR
OUTCOM + INNCOM CAP MICROCONTROLLER REFL SDI SCLK ENA 0.1F CONTROL IF +2V
VCOM RF
RD_WRBAR
SDO
EXT_OSC
LCD TIMING CONTROLLER
HORIZONTAL RATE
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EL5625 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21, 30 22 23, 29 24 25 26 27 28 31 32 33 34 35 36 37 38 PIN NAME OUTA LDO_COMP LDO_IN VSD SDI SCLK ENA SDO RD_WRBAR EXT_OSC RESET OUTR OUTQ OUTP OUTO OUTN OUTM OUTL OUTK OUTJ VS OUTCOM GND INNCOM REFL REFH LDO_OUT CAP OUTI OUTH OUTG OUTF OUTE OUTD OUTC OUTB PIN TYPE Analog Output Analog Input Analog Input Power Logic Input Logic Input Logic Input Logic Output Analog Input Input/Output Analog Input Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Power Analog Output Power Analog Input Analog Input Analog Input Analog Output Analog Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Channel A output voltage LDO compensation capacitor LDO inverting input Positive power supply for digital circuits (3.3V - 5V) Serial data input Serial data clock Chip select, low enables data input to logic Serial data output Read, write select: "0" = write, "1" = read Oscillator pin for synchronizing Reset all registers: "0" = reset Channel R output voltage Channel Q output voltage Channel P output voltage Channel O output voltage Channel N output voltage Channel M output voltage Channel L output voltage Channel K output voltage Channel J output voltage Positive supply voltage for analog circuits (4.5V - 16.5V) VCOM output Ground VCOM inverting input Low reference voltage High reference voltage LDO output Decoupling capacitor for internal reference Channel I output voltage Channel H output voltage Channel G output voltage Channel F output voltage Channel E output voltage Channel D output voltage Channel C output voltage Channel B output voltage PIN DESCRIPTION
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FN7488.0 February 28, 2006
EL5625 Typical Performance Curves
VS=VREFH=15V VS=VREFH=15V
0mA
5mA
5mA CL=1nF 200mV/DIV CL=4.7nF CL=180pF M=400ns/DIV
0mA CL=180pF CL=4.7nF 200mV/DIV CL=1nF M=400ns/DIV
FIGURE 1. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 2. TRANSIENT LOAD REGULATION (SINKING)
SCLK SDI
SCLK SDI ENA OUTA
ENA
OUTA
M=400s/DIV
M=400s/DIV
FIGURE 3. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V)
FIGURE 4. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV)
3.5 POWER DISSIPATION (W) 3 2.5 2 1.5 1 0.5 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD LPP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 QFN38 JA=30C/W POWER DISSIPATION (W)
1 0.8 0.6 0.4 0.2 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
3.33W
QFN38 0.80W JA=125C/W
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7488.0 February 28, 2006
EL5625 General Description
The EL5625 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 11 bits of resolution. Ref-High and Ref-Low pins determine the high and low voltages of the output range. These outputs can be driven to within 50mV of the power rails of the EL5625. Programming of each output, 18 buffers and 1 Vcom, is performed using the USB interface.
BIT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 TABLE 1. CONTROL BITS LOGIC TABLE NAME A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION Channel Address Channel Address Channel Address Channel Address Channel Address Data Data Data Data Data Data Data Data Data Data Data
USB Interface
The EL5625 uses USB interface to control the 18 Gamma channels and Vcom channel (Figure 7). Software is available for download on Intersil's website.
FIGURE 7. USB INTERFACE
Serial Interface
The EL5625 is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are allocated to the following functions (also refer to the Control Bits Logic Table). * Bits 15 through 11 select the channel to be written to, these are binary coded with channel A = 0, and channel R = 17 * The 11-bit data is on bits 10 through 0. Some examples of data words are shown in the table of Serial Programming Examples
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FN7488.0 February 28, 2006
EL5625 Serial Timing Diagram
ENA
tHE
tSE
T
tr
tf
tHE
tSE
SCLK tSD tHD tw
SDI
B15 MSB
B14
B13
B12-B2
B1
B0 t LSB
LOAD MSB FIRST, LSB LAST
TABLE 2. SERIAL TIMING PARAMETERS PARAMETER T tr/tf tHE tSE tHD tSD tW RECOMMENDED OPERATING RANGE 200ns 0.05 * T 10ns 10ns 10ns 10ns 0.50 * T Clock Period Clock Rise/Fall Time ENA Hold Time ENA Setup Time Data Hold Time Data Setup Time Clock Pulse Width DESCRIPTION
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back plate of an LCD display. This plate is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rates for the display. Thus the amplifier must be capable of sourcing and sinking capacitive pulse of current, which can be quite large (100mA for typical applications).
CLOCK OSCILLATOR The EL5625 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labelled EXT_OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the EXT_OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the EXT_OSC pin will be in a high impedance condition to prevent contention. By setting pin 10 to high, the chip is on external clock mode. Setting pin 10 to low, the chip is on internal clock mode.
Analog Section
TRANSFER FUNCTION The transfer function is:
data V OUT ( IDEAL ) = V REFL + ------------ x ( V REFH - V REFL ) 2048
where data is the decimal value of the 11-bit data binary input code. The output voltages from the EL5625 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5625. GND < VREFH VS and GND VREFL VREFH.
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FN7488.0 February 28, 2006
EL5625
CHANNEL OUTPUTS Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48s. In the worst-case scenario, this will be 860s for EL5625, when the data has just missed the cycle at f_OSC = 21kHz. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 6.8ms and 7.2ms depending on the absolute timing relative to the update cycle. at the rising edge of the OSC signal. Since at the rising edge of the OSC clock, the refreshed switches are being opened, if the load changes at that time, it will generate an error output voltage. For a fixed load condition, the internal oscillator can be used. For the transient load condition, the external OSC mode should be used to avoid the conflict between the rising edge of the OSC signal and the changing load. So a timing delay circuit will be needed to delay the OSC signal and avoid the rising edge of the OSC signal and changing the load at the same time. TRANSIENT LOAD RESPONSE
Output Stage and the Use of External Oscillator
Simplified output sample and hold amp stage for one channel.
CH 1.3V + S1
FIGURE 9.
Channel 3 --- sinking and sourcing 5mA current Channel 2 --- EXT_OSC signal Channel 1 --- VOUT Here, the OSC signal is synchronized to the load signal. The rising edge of the OSC signal is then delayed by some amount of time and gives enough time for CH to be charged to a new voltage before the switches are opened. CHANNEL TO CHANNEL REFRESH
+ 1.3V S2 OSC
VOUT
VIN
+ -
FIGURE 8.
The output voltage is generated from the DAC, which is VIN in the above circuit. The refreshed switches are controlled by the internal or external oscillator signal. When the OSC clock signal is low, switches S1 and S2 are closed. The output VOUT = VIN and at the same time the sample and hold cap CH is being charged. When the OSC clock signal is high, the refreshed switches S1 and S2 are opened and the output voltage is maintained by CH. This refreshed process will repeat every 18 clock cycles for each channel. The time takes to update the output depends on the timing at the VIN and the state of the switches. It can take 1 to 19 clock cycles to update each output. For the sample and hold capacitor CH to maintain the correct output voltage, the driving load shouldn't be changed 9
FIGURE 10.
Ch1 --- Output1 Ch3 --- Output2 Ch2 --- EXT_OSC
FN7488.0 February 28, 2006
EL5625
At the falling edge of the OSC, output 1 is being refreshed and one clock cycle later, output 2 is being refreshed. The spike you see here is the response of the output amplifier when the refreshed switches are closed. When driving a big capacitor load, there will be ringing at the spikes because the phase margin of the amplifier is decreased. The speed of the external OSC signal shouldn't be greater than 70kHz because for the worst condition, it will take at least 4s to charge the sample and hold capacitor CH. The pulse width has to be at least 4s long. From our lab test, the duty cycle of the OSC signal must be greater than 30%. POWER DISSIPATION With the 100mA maximum continues output drive capability for VCOM channel, it is possible to exceed the 125C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
when sourcing, and:
P DMAX = V S x I S + ( V OUT i x I LOAD i )
when sinking. Where: * i = 18 * VS = Supply voltage * IS = Quiescent current * VOUTi = Output voltage of the i channel * ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. THERMAL SHUTDOWN The EL5625 has an internal thermal shutdown circuitry that prevents overheating of the part. When the junction temperature goes up to about 150C, the part will be disabled. When the junction temperature drops down to about 120C, the part will be enabled. With this feature, any short circuit at the outputs will enable the thermal shutdown circuitry to disable the part. POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5625. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5625 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1F ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7F local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins.
where: * TJMAX = Maximum junction temperature * TAMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads.
P DMAX = V S x I S + [ ( V S - V OUT i ) x I LOAD i ]
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7488.0 February 28, 2006
EL5625
QFN Package Outline Drawing
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FN7488.0 February 28, 2006

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